The present invention relates to a multi-level decision circuit for use in a digital communication system utilizing a multi-level modulated signal, and more particularly to a multi-level decision circuit which is supplied with a multi-level signal of 2.sup.M levels (M being an integer equal to or greater than 2) and decides which one of the 2.sup.M levels the input multi-level signal belongs to.
Known as a digital transmission system using the microwave band is a 16 QAM (Quadrature Amplitude Modulation) system. With this system, binary digital signals of two sequences A.sub.1 and A.sub.2 are converted by a DA converter into a 4-level digital signal using the signal A.sub.1 as a high-order bit of a 2-bit binary signal and the signal A.sub.2 as a low-order bit thereof. A carrier is amplitude modulated by the 4-level digital signal. In the meantime, binary digital signals of two sequences B.sub.1 and B.sub.2 are similarly converted into a 4-level digital signal, by which is amplitude modulated a carrier displaced 90 degrees apart in phase from the abovesaid carrier. The both amplitude-modulated outputs are combined into a composite signal for transmission. At the receiving side, the received signal is coherently detected by recovered carriers phased 90 degrees apart, by which the abovesaid two 4-level digital signals are demodulated. These 4-level digital signals are respectively converted by AD converters into binary digital signals, thus obtaining the aforementioned binary digital signals A.sub.1, A.sub.2 and B.sub.1, B.sub.2.
A multi-level quadrature amplitude modulation system has been proposed in which, in general, M (M being an integer equal to or greater than 2) bit binary digital signals are converted to a 2.sup.M -level digital signal and carriers are modulated by such 2.sup.M -level digital signals of two sequences into a QAM signal. With such a multi-level amplitude modulation system, in order to correctly decide the multi-level amplitude signal at the receiving side, it is necessary that the levels of the multi-level amplitude signal input to a decision circuit be held in level regions predetermined in accordance with the number of levels. If the DC level of the input multi-level amplitude signal fluctuates, then the probability that the (M+1)th bit from MSB of the AD converter output (those bits from MSB to the Mth one being decided outputs) becomes mark "1" deviates from 50%. In order to detect and eventually eliminate the deviation, a DC signal which is supplied to a DC amplifier provided in the preceding stage of the AD converter is subjected to feedback control so that the DC level at the output of the DC amplifier assumes a reference value. This is disclosed in the Japanese Patent Application Laid Open No. 58-101449, published on June 16, 1983. Further, it has been proposed in the Japanese Patent Application Laid Open No. 57-131152, published on Aug. 13, 1982 that the gain of the DC amplifier is feedback-controlled by the output of the AD converter so that the variation in the level of the DC amplifier output comes to agree with a predetermined value.
Accordingly, it is considered that the input multi-level amplitude signal could correctly be decided by simultaneously effecting the control of DC level and gain. As a result of the present inventors' experiments and researches, however, it has been found out that this method cannot prevent the occurrence of errors, too. The reason for this is that if the DC level of the multi-level amplitude signal at the input side of the AD converter shifts upward or downward by an integral multiple of the interval between adjacent levels, the feedback control could be stabilized in that state. Such a stable state is called a false lock state.